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Semiconductor
May 1999
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CD22402
Generator for TV Applications and Video Processing Systems
Features
* Interlaced Composite Sync Output
Description
The Harris CD22402 (Note) is a CMOS LSI sync generator that produces all the timing signals required to drive a fully 2-to-1 interlaced 525-line 30-frame/second, or 625-line 25-frame/second TV camera or video processing system. A complete sync waveform is produced which begins each field with six serrated vertical sync pulses, preceded and followed by six half-width double frequency equalizing pulses. The sync output is gated by the master clock to preserve horizontal phase continuity during the vertical interval. The CD22402 can be operated either in "genlock" mode, in which it is synchronized with a reference sync pulse train from another TV camera, or in "stand-alone" mode, in which it is synchronized with a local on-chip crystal oscillator (the crystal and two passive components are off chip). Also, the circuit can sense the presence or absence of a reference sync pulse train and automatically select the "genlock" or "stand-alone" mode. A frame sync pulse is produced at the beginning of every odd field. The vertical counter can be reset to either the first equalizing pulse or the first vertical sync pulse of the vertical interval. The interlaced sync provided by the CD22402 differs from RS-170 by having slightly narrower sync and equalizing pulses. The clock frequency of 32 times horizontal rate allows for approximately 4s horizontal pulse widths and 2s equalizing pulses. Otherwise operation can be phase locked to a color sub-carrier for a full interlaced operating system. The CD22402 is operable with a single supply over a voltage range of 4V to 15V.
[ /Title (CD2240 2) /Subject Sync eneraor for V pplicaions and ideo rocess-
* Automatic Genlock Capability * Crystal Oscillator Operation * 525 or 625 Line Operation * Vertical Reset Option * Wide Power Supply Operating Voltage . . . . . 4V to 15V
Applications
* Cameras * Monitors and Displays * CATV * Teletext * Video Games * Sync Restorer * Video Service Instruments
Part Number Information
PART NUMBER CD22402D CD22402E TEMP. RANGE (oC) -55 to 125 -40 to 85 PACKAGE 24 Ld SBDIP 24 Ld PDIP PKG. NO. D24.6 E24.6
Pinout
CD22402 (PDIP, SBDIP) TOP VIEW
DELAY, GENLOCK TO CRYSTAL OSCILLATOR CRYSTAL OSCILLATOR FEEDBACK TAP VSS HORIZONTAL DRIVE OUTPUT MIXED SYNC OUTPUT GENLOCK OSCILLATOR CAPACITOR CONNECTION MIXED BEAM BLANKING OUTPUT VERTICAL COUNTER RESET TO FIRST EQUALIZING PULSE VERTICAL DRIVE OUTPUT VERTICAL RESET TO FIRST VERTICAL SYNC PULSE HORIZONTAL CLAMP OUTPUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RESISTOR CONNECTION FOR GENLOCK OSCILLATOR MASTER FREQUENCY INPUT R-C CONNECTION FOR GENLOCK OSCILLATOR DELAY, GENLOCK TO CRYSTAL OSCILLATOR GENLOCK INPUT (COMPOSITE SYNC) VDD 525 LINE TO 625 LINE OPERATION SWITCH VERTICAL PROCESSING BLANKING OUTPUT SHORT VERTICAL DRIVE OUTPUT FRAME SYNC OUTPUT (ODD FIELD) HORIZONTAL PROCESSING BLANKING OUTPUT MIXED PROCESSING BLANKING OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1999
File Number
1686.5
8-40
CD22402 Pin Descriptions
PIN NO. 1 SYMBOL XRC DESCRIPTION Delay, Genlock to Crystal Oscillator. Resistor, diode and capacitor connection for delay that automatically turns on the crystal oscillator when the genlock input is removed. When the signal on Terminal 1 is high the crystal oscillator is inhibited. Typical values for R and C are 1M and 0.001F. For operation as a crystal controlled stand alone sync generator without genlock, Terminal 1 should be hardwired to VSS. Crystal Oscillator Feedback Tap. Feedback connection (tap) for crystal oscillator. When a crystal (shunted by a 1M resistor) is connected between this terminal and Terminal 23, and a 100pF capacitor is connected from this terminal to VSS, the sync generator creates its own master frequency. For a 525-line, 30-frame/second raster, the crystal frequency is 504.000kHz (Note 1); and for a 625-line, 25-frame/second raster, the crystal frequency is 500.000kHz (Note 1). Negative Power Supply Voltage. This terminal must be hardwired to Terminal 12 (VSS). Horizontal Drive Output Mixed Sync Output Capacitor Connection for R-C Genlock Oscillator Mixed Beam Blanking Output Vertical Counter Reset to First Equalizing Pulse. A low level signal on this terminal resets the vertical counter to the first equalizing pulse of a field. When not in use this terminal should be connected to VDD. Vertical Drive Output Vertical Counter Reset to First Vertical Sync Pulse. A low level signal on this terminal resets the sync generator to the first vertical sync pulse of a field. For genlock operation, Terminal 10 is used as a resistor and capacitor connection for an integrator network that detects vertical sync pulses in a master sync waveform to which the sync generator is to be genlocked. R is 22k, and C is 0.001F. When not in use this terminal should be connected to VDD. Horizontal Clamp Output Negative Power Supply Voltage Mixed Processing Blanking Output Horizontal Processing Blanking Output Frame Sync Output (Odd Field). A pulse coinciding with the first equalizing pulse is produced at the beginning of every odd field. Short Vertical Drive Output Vertical Processing Blanking Output Operation Switch for 525-Line or 625-Line Raster. A high level signal on Terminal 18 causes the sync generator to generate a 625-line raster. An internal pulldown resistor is connected to Terminal 18, so in the absence of an applied input to this terminal, a 525-line raster is produced. Positive Power Supply Voltage. VDD can be any voltage between +4 and +15 relative to VSS . Genlock Input Composite Sync. A negative going reference mixed sync waveform applied to Terminal 20 disables the crystal oscillator and locks the R-C genlock oscillator to the horizontal pulses of the reference sync waveform. Vertical sync detection is achieved by an R-C integrator connected from Terminal 20 to Terminal 10 (vertical reset to first vertical sync pulse). An internal pull-up resistor is connected to Terminal 20 so that in the absence of an applied input the crystal oscillator is enabled and the R-C genlock oscillator is disabled. Delay, Genlock to Crystal Oscillator, Resistor and Diode Connection for Delay, Genlock to Crystal Oscillator. Automatically turns on the crystal oscillator when the input to Terminal 20 is removed. Resistor and Capacitor Connection for Genlock Oscillator. If the genlock oscillator is not used this terminal should be connected to VSS. C should be 100pF, and R should be a 10k potentiometer. Master Frequency Input. Resistor Connection for Genlock Oscillator.
2
XTP
3 4 5 6 7 8 9 10
VSS HD MS C MBB VRE VD VRV
11 12 13 14 15 16 17 18
HC VSS MPB HPB FS2 SVD VPB SW
19 20
VDD GEN
21 22 23 24
XR RC XIN R
NOTE: 32 times horizontal frequency.
8-41
CD22402 Block Diagram
CD22402 MONOCHROME TV SYNC GENERATOR WITH AUTOMATIC GENLOCK
R 24 RC 22 C 6 VRE 8 SW 18
VRV
10
R-C GENLOCK OSCILLATOR
HORIZONTAL COUNTER
VERTICAL COUNTER
/16
/525/625
GEN XR
20 21 AUTOMATIC GENLOCK CONTROL 1
/2
LINE DECODER FIELD DECODER
XRC
COMPOSITE DECODER XIN 23 CRYSTAL OSCILLATOR 2 FRAME SYNC DECODER
XTP
VSS = PINS 3 AND 12 VDD = PIN 19
14 HPB
11 HC
4 HD
5 MS
13
7
15 FS2
16 SVD
9
17
MPB MBB
VD VPB
8-42
CD22402
Absolute Maximum Ratings
DC Supply Voltage (Referenced to VSS Terminal) . . . . . . . . . . . 15V Input Voltage Range, All Inputs (Notes 2, 3) . . . . . . VSS VI VDD DC Input Current, Any One Input (Note 2) . . . . . . . . . . . . . . 10mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 50 10 PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A Maximum Junction Temperature (SBDIP Package) . . . . . . . . 175oC Maximum Junction Temperature (PDIP Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range CD22402D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CD22402E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS. Input currents must not exceed 10mA even when the power is off. 3. A connection must be provided at every input terminal. All unused inputs must be connected to VDD or VSS, whichever is appropriate.
Electrical Specifications
Values at -55oC, 25oC, 125oC Apply to D Package Values at -40oC, 25oC, 85oC Apply to E Package TEST CONDITIONS 25oC -55oC -40oC 85oC 125oC MIN TYP MAX UNITS
PARAMETER
SYMBOL
VO (V)
VDD (V)
DC ELECTRICAL SPECIFICATIONS Quiescent Device Current IDD (Max) Output Low (Sink) Current IOL (Min) 0.5 5 0.5 10 Output High (Source) Current IOH (Min) 4.5 0 9.5 0 Output Voltage Low Level VOL (Max) Output Voltage High Level VOH (Min) Input Low Voltage VIL (Max) 0.5, 4.5 1, 9 Input High Voltage VIH (Min) 0.5, 4.5 1, 9 Input Current IIN (Max) 5 10 15 5 5 10 10 5 5 10 10 5 10 5 10 5 10 5 10 100 1200 248 3000 -100 -1200 -248 -3000 0.15 0.15 4.85 9.85 1.5 3 3.6 7.1 96 1155 239 2868 -96 -1155 -239 -2868 0.15 0.15 4.85 9.85 1.5 3 3.6 7.1 66 787 164 1968 -66 -787 -164 -1968 0.15 0.15 4.85 9.85 1.4 2.9 3.5 7 56 672 140 1680 -56 -672 -140 -1680 0.15 0.15 4.85 9.85 1.4 2.9 3.5 7 0.5 1.5 3 80 960 200 2400 -80 -960 -200 -2400 4.85 9.85 3.5 7 0.75 2 4 160 1920 400 4800 -160 -1920 -400 -4800 2.25 4.5 2.25 4.5 10 1 2.5 5 0.15 0.15 1.5 3 mA mA mA A A A A A A A A V V V V V V V V pA
Refer to the CD4000B Series data book 250.5 for general operating and application considerations.
8-43
CD22402
Switching Electrical Specifications
TA = 25oC and CL = 15pF. Typical Temperature Coefficient for All Values of VDD = 0.3%/oC TEST CONDITIONS PARAMETER (NOTE 4) Output State Propagation Delay Time (50% to 50%) Low-to-High Level High-to-Low Level Output State Transition Time (10% to 90%) Low-to-High High-to-Low Input Capacitance (Per Input) NOTE: 4. The characteristics given are defined for unbuffered gate in the CMOS process of the CD22402. tTLH tTHL CI 5 10 45 30 5 90 60 ns ns pF tPLH tPHL 5 10 40 20 80 40 ns ns SYMBOL VDD (V) MIN TYP MAX UNITS
Logic Diagram
VERTICAL DRIVE (VERT. RESET TO FIRST VERT. PULSE) INTEGRATOR 10 + R S Q Q GENLOCK OSC. 22 10K 10K 24
51pF 6
GENLOCK SYNC
20 HOR. DR
S R
Q Q
(NOTE 5) 21 1M 1N914 1 0.001F (NOTE 6) 23 1M 2 HOR. PROCESS BLANKING CLOCK TO COUNTERS
CRYSTAL 32 TIMES HORIZ. 503.496kHz 100pF
NOTES: 5. Pin 21 high when pin 20 is high (or open). 6. Pin 1 high inhibits clock. FIGURE 1. DETAIL OF THE OSCILLATOR/GENLOCK PORTION OF THE CD22402
8-44
CD22402 Timing Waveforms
MICROSECONDS 504kHz OSC. PIN 2 OR 6 MIXED BLANKING PIN 13 0 1.98 3.97 5.95 7.94 9.92 11.90 27.78 31.75 33.73
11.9s
HORIZ. DRIVE PIN 4 MIXED BEAM (CATHODE) BLANKING PIN 7
3.97s
7.94s
1.98s HORIZ. CLAMP PIN 11 3.97s H. SYNC 1.98s MIXED SYNC PIN 5 EQUALIZING PULSE 25.8s V. SYNC 3.97s 1.98s
FIGURE 2. SYNC GENERATOR TIMING - 525/60Hz, HORIZONTAL TIMING WAVEFORMS
TO FIRST EQUALIZING PULSE LINE NO MIXED SYNC PIN 5 0 1 2 3 4
VERTICAL RESET TO FIRST VERTICAL PULSE 5 6 7 8 9 10 21
VERT. DRIVE PIN 9 VERTICAL PROCESSING BLANKING PIN 17
0.57ms
1.33ms WIDE BLANKING PIN 13 0.19ms SHORT VERTICAL DRIVE PIN 16 MIXED BEAM (CATHODE) BLANKING PIN 7 FRAME SYNC PIN 15 (ON ALTERNATE FIELDS) 1.98s (NOT TO SCALE)
FIGURE 3. SYNC GENERATOR TIMING - 525/60Hz, VERTICAL TIMING WAVEFORMS
8-45
CD22402 Timing Waveforms
MICROSECONDS 500kHz OSC. PIN 2 OR 6 MIXED BLANKING PIN 13 4s 0
(Continued)
2 4 6 8 10 12 28 32
12s
HORIZ. DRIVE PIN 4 CATHODE BLANKING PIN 7
8s
2s HORIZ. CLAMP PIN 11 4s H. SYNC 2s MIXED SYNC PIN 5 EQUALIZING PULSE 26s V. SYNC 4s 2s
FIGURE 4. SYNC GENERATOR TIMING - 625/50Hz, HORIZONTAL TIMING WAVEFORMS
VERTICAL RESET TO FIRST VERTICAL PULSE 0 1 2 3 4 5 6 7 8 9 10 21
VERTICAL RESET TO FIRST EQUALIZING PULSE LINE NO MIXED SYNC PIN 5
VERT. DRIVE PIN 9 VERTICAL PROCESSING BLANKING PIN 17
0.57ms
1.36ms WIDE BLANKING PIN 13 0.194ms SHORT VERTICAL DRIVE PIN 16 CATHODE BLANKING PIN 7 FRAME SYNC PIN 15 (ON ALTERNATE FIELDS) 2s (NOT TO SCALE)
FIGURE 5. SYNC GENERATOR TIMING - 625/50Hz, VERTICAL TIMING WAVEFORMS
8-46
CD22402 Timing Waveforms
FIELD NO. 1 PIN 5
(Continued)
LINE 0 FIRST EQUALIZING PULSE LINE 9
1 CLK PIN 9
2 CLKS
2 CLKS FIELD NO. 2 PIN 5 LINE 262-1/2 (312-1/2)
2 CLKS LINE 271 (321)
PIN 9
1 CLK
1 CLK
2 CLKS SEE NOTES 1, 2
14 CLKS
FIGURE 6. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (VERTICAL DRIVE - PIN 9)
FIELD NO. 1 PIN 5
LINE 0 FIRST EQUALIZING PULSE
LINE 21
1 CLK PIN 17
2 CLKS
2 CLKS FIELD NO. 2 LINE 262-1/2 (312-1/2) PIN 5 LINE 283 (333)
2 CLKS
1 CLK PIN 17
2 CLKS
2 CLKS SEE NOTES 1, 2
14 CLKS
FIGURE 7. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (VERTICAL PROCESSING BLANKING - PIN 17)
8-47
CD22402 Timing Waveforms
FIELD NO. 1 PIN 5 LINE 0 FIRST EQUALIZING PULSE
(Continued)
LINE 21
1 CLK PIN 13
2 CLKS 1 CLK
FIELD NO. 2
2 CLKS LINE 262-1/2 (312-1/2)
1 CLK 6 CLKS LINE 283 (333)
PIN 5
PIN 13
1 CLK
2 CLKS
2 CLKS SEE NOTES 1, 2
14 CLKS
FIGURE 8. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (MIXED PROCESSING BLANKING - PIN 13)
FIELD NO. 1 PIN 5
LINE 3
LINE 6
1 CLK 2 CLKS PIN 16 2 CLKS
FIELD NO. 2 LINE 265-1/2 (315-1/2) PIN 5 LINE 268-1/2 (318-1/2)
PIN 16
2 CLKS SEE NOTES 1, 2
2 CLKS
FIGURE 9. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (SHORT VERTICAL DRIVE - PIN 16)
8-48
CD22402 Timing Waveforms
PIN 5
(Continued)
LINE 3 LINE 6 LINE 7
LINE 2
1 CLK PIN 7
15 CLKS
4 CLKS LINE 265 (315) PIN 5
2 CLKS LINE 265-1/2 (315-1/2)
2 CLKS LINE 268-1/2 (318-1/2)
4 CLKS LINE 269 (319)
1 CLK PIN 7
15 CLKS
4 CLKS
2 CLKS SEE NOTES 7, 8
2 CLKS 16 CLKS
NOTES: 7. Waveforms shown are for 525 line/60Hz, line number in parenthesis are for (625 line/50Hz). 8. Timing widths by clock count; for 525 line, 1 CLK = 1.98s; for 625 line, 1 CLK = 2s; 1 horizontal period = 32 CLKS. FIGURE 10. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (MIXED BEAM BLANKING - PIN 7)
Typical Applications (Refer to Application Note AN8742, for more information)
HORIZ. PHASE ADJ. HORIZ. MIXED SYNC. OR COMPOSITE VIDEO INPUT VERTICAL SYNC (OPTIONAL) FROM SHORT VERTICAL DRIVE 100pF 22 GEN LOCK OSC. PLL 1 AUTO GEN LOCK CONTROL 1M 21 23 1M CRYSTAL OSC. 100pF 2 3, 12 15 17 18 FRAME SYNC OUTPUT (ODD FIELD) VERTICAL PROCESSING BLANKING OUTPUT OPERATION SWITCH FOR 525-LINE OR 625-LINE RASTER 5 MIXED SYNC 10k 24 16 SHORT VERTICAL DRIVE 9 VERTICAL DRIVE SYNC RESTORER VERT. 10 8 6 VDD
20 19 4 11 7 13 14 HORIZONTAL DRIVE HORIZONTAL CLAMP MIXED BEAM (CATHODE) BLANKING MIXED PROCESSING BLANKING HORIZONTAL PROCESSING BLANKING
FROM POWER LINE FOR LINE-LOCK OPERATION
ZERO CROSSING DETECTOR
FIGURE 11. TYPICAL APPLICATION IN A TV CAMERA
8-49
CD22402
13 100k 3.3F 10k 75 1k 2 3 12
4 +
14 NEG. HORIZ. SYNC OUT (TO PIN 20 - CD22402)
1 +
1
0.1F 100k 0.0022F 1N914 2M
5 6
+ 2
7 10k POS. HORIZ. SYNC OUT
-
0.5 TO 2VP-P VIDEO SIGNAL IN VSS VDD 2k VCC = +5 10F GND 2k 10F
0.0022F
10k 9 8 NEG. VERTICAL SYNC OUT (TO PIN 10 - CD22402)
0.0022F
10
3 +
CA5470 BIMOS-E QUAD OP AMP PIN 4 TO +5V (VDD) PIN 11 TO GND (VSS)
NOTE: The genlock input to pins 10 and 20 of the CD22402 are direct coupled to the output from Pins 8 and 14 of the CA5470. Refer to Application Note AN-8742 for additional information. FIGURE 12. SUGGESTED SYNC-SEPARATOR CIRCUIT USING THE CA5470 BIMOS-E QUAD OP AMP IN THE VDD RANGE OF 4V TO 12V
8-50

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